+ ad include anlog simulation interface and library + acc enable pli applications to use acc routines (see manual) y libdir search for unresolved module references in directory 'libdir' v file search for unresolved module references in 'file' u treat all non text string characters as uppercase o exec name the executable simulation model 'exec' (default is 'simv') syslib 'libs' specify system libraries (placed last on the link line) eg -lm display name of vcs installation subdirectory for this platform. mhdl include MixedHDL-2.0 interface and library vhdlobj generate a vhdl obj for simulating in a vhdl design location display full pathname to vcs installation for this platform. vera_dbind add VERA 4.5+ libraries for dynamic binding lmc-hm include lmc hardware modeler interface line enable single-stepping / breakpoints for source level debugging ( refer vcs manual for compatibility with -cpp option) gen_obj generate native object code (HP and Sun only) gen_asm generate native assembly code (HP and Sun only) gen_c generate C code (for HP and Sun, default is -gen_obj) (see manual section 7-11 for more details). e specify the name of your main () routine. V verbose mode with 't', include time information RPP run xvcs in postprocessing mode (requires file created by vcdpluson) RIG run simulation under xvcs without compiling (executable has to exist) RI after compilation, run simulation under xvcs (Implies -I) R after compilation, run simulation executable PP enable optimizer postprocessing capabilities for vcd + P plitab compiles user-defined pli definition table 'plitab' Marchive create intermediate libs to reduce link line length N objs per lib Mupdate enable incremental compilation and keep the Makefile up-to-date M enable incremental compilation (see manual) I enable interactive / postprocessing debugging capabilities LDFLAGS "opts" pass 'opts' to C compiler on load line only B generate long call instructions in native assembly code (HP only) ASFLAGS "opts" pass 'opts' to the assembler Not perform timing check but still add path delay to the simulation + nospecify does not perform timing check and path delay calculation on SPECIFY module + notimingcheck does o Specify the output executable file Name, the default is simv notice Display detailed diagnostic information P pli.tab Define the PLI list (Tab) file + incdir + directory + add include folders + define + macro = value + precompiled macros The -cm Line | cond | FSM | TGL | OBC | coverage path set way Vcs commonly used command options are as follows: The -R command means that it will be executed immediately after compilation. Similar to NC, there is also a single command line: vcs source_files -R Compile the verilog file into an executable binary file The command is: vcs source_files VCS simulation of the verilog model includes two steps: 1.
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